1. Field of the Invention
The present invention relates to a semiconductor device including a ferroelectric nonvolatile memory which utilize ferroelectric properties.
2. Description of the Prior Art
Some semiconductor devices which are conventionally known comprise semiconductor nonvolatile memories. A floating-gate type memory cell and MNOS a (Metal-Nitride-Oxide-Semiconductor) type memory cell are well known as one type of nonvolatile memory. But U.S. Pat. No. 3,832,700 discloses a nonvolatile memory which utilizes ferroelectric properties: remanence and reversibly dielectric polarization. Such a ferroelectric nonvolatile memory is characterized in that the speed of its operation for writing and erasing is high.
FIG. 4 shows the memory cell 1 of this ferroelectric nonvolatile memory in schematic sectional view.
Referring to FIG. 4, a N+ type drain 6 and a N+ type source 8 are created in P type silicon substrate 10. A film 4 of ferroelectric material spans the space 12 between the drain 6 and the source 8. On top of the ferroelectric film 4 is a conductive metalization 2 such as aluminum which acts as a control electrode. Note that the space 12 is referred to as channel region hereinafter.
A logic "1" can be written into and erased from the above-mentioned memory cell 1 by electricity. Accordingly, the memory cell 1 has two stable states: one in which a logic "1" has been written therein, and the other in which the logic "1" has been erased or a logic "0" has been stored therein. The fact that the memory cell 1 can take these two stable states is utilized to fabricate a memory.
FIG. 5 shows hysteresis loop which the memory cell 1 exhibits. Referring to FIG. 5, the vertical axis represents polarization P and horizontal axis represents electric field E. There will be described the way in which the logic "1" is able to be written into and erased from the memory cell 1 with reference to FIG. 5.
In order to write a logic "1" into a memory cell 1, ground potential is applied to the substrate 10 and more programming voltage than positive coercive voltage is applied to the control electrode 2. Note that the coercive voltage is a voltage applied to the control electrode 2 with which the memory cell 1 can remove the existing negative polarization of the film 4. At that time, an electric field develops between the substrate 10 and the control electrode 2 and thereby the ferroelectric film 4 is polarized into a direction parallel to the electric field, as symbolized by point P1 in FIG. 5. In addition, this polarization will remain as it is even if the gate voltage is cut off, as symbolized by point Q1 in FIG. 5.
This status in polarization of the ferroelectric film 4 mean that a logic "1" has been written into the memory cell 1. In the memory cell 1 having the logic "1", the channel region 12 is conductive because a portion of the ferroelectric film near the control electrode 2 is in charge of the negative and a portion of the ferroelectric film 4 near the substrate 10 is in charge of the positive.
On the other hand, in order to erase the logic "1" from the memory cell 1 or to write a logic "0" therein, ground potential is applied to the substrate 10 and less programming voltage than negative coercive voltage is applied to the control electrode 2. At that time, an electric field of the opposite polarity to that used when writing the logic "1" between the substrate 10 and the control electrode 2 and thereby the ferroelectric film 4 is polarized into the direction parallel to the electric field, as symbolized by point R1 in FIG. 5. In addition, this polarization will remain as it is even if the gate voltage is cut off, as symbolized by point S1 in FIG. 5.
This status in polarization of the ferroelectric film 4 means that the logic "1" has been erased or a logic "0" has been written into the memory cell 1. In the memory cell 1 with the logic "0", the channel region 12 is nonconductive because a portion of the ferroelectric film 4 near the control electrode 2 is in charge of the positive and a portion of the ferroelectric film near the substrate is in charge of the negative.
The operation of reading information from a memory cell 1 will be described below. It is determined whether the memory cell 1 has a logic "0" or a logic "1", by determining whether or not a current flows through the channel region 12 when a stable voltage is applied to the source 8 relative to the drain 6 of the memory cell 1.
A ferroelectric nonvolatile memory (not shown) can be constructed using the memory cells 1 described above.
However, semiconductor devices including such memory devices have the following problems.
The problem lies in the border between the channel region 12 and the ferroelectric film 4 because the ferroelectric film 4 is deposited directly on the substrate 10. Specifically, the surface of the channel region 12 is oxidized when the ferroelectric film 4 is deposited on the substrate 10. This oxidized surface hinders operation at lower voltage because it lower the relative power of field effect applied to the ferroelectric film when a certain programming voltage is applied to the control electrode relative to the substrate 10.
Also, components such as a metallic component of the ferroelectric film is diffused to the channel region 12 of silicon during the manufacturing process of memory circuit. In other word, the desired clean surface of the channel region 12 was not obtained. In this case, the memory constructed by using the memory cell 1 was not able to operate correctly.